Principal ASIC Physical Design Engineer

K2 Space Corporation·Seattle, WA·30 июня

Principal ASIC Physical Design Engineer

🏢 ОфисLeadПолная занятость

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Наша компания

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an

О роли

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

Чем предстоит заниматься

Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off

Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA)

Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration

Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools

Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration

Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards

Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies

Support chip bring-up and debug through close collaboration with post-silicon and test teams

Support your product through production and spaceflight

Наши требования

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field

10+ years of experience in ASIC physical design for high-performance SoCs

Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)

Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation

Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs

Experience with advanced FinFET process nodes

Prior experience managing or coordinating offshore/outsourced PD teams or vendors

Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF)

Excellent communication, leadership, and cross-functional collaboration skills

Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team

Exposure to radiation-hardened or space-qualified ASICs

Experience with chip-package co-design or advanced packaging (2.5D/3D)

Familiarity with physical design service vendor management or offshore collaboration

Experience driving tapeouts through TSMC

Experience with Gate-All-Around technologies

Experience working in cross-functional, geographically distributed teams

Мы предлагаем

Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level

Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

Export Compliance

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”

Дополнительно

Base salary range for this role is $190,000 – $280,000 + equity in the company

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space

K2 Space Corporation

Seattle, WA

ГрейдLead

ЗанятостьПолная занятость

РегионНе Россия

ФорматОфис

ИсточникСкрыто

Опубликовано30 июня

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