Наши требования
Experience with SI/PI verification and sign-off methodologies
Familiarity with thermal modeling and co-simulation for integrated packages
Exposure to AI accelerator or custom ASIC design flows
Experience collaborating with OSAT partners, substrate vendors, or research institutes (e.g., imec)
Knowledge of advanced node custom and analog design practices
Location
Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus
7+ years of experience in power delivery and/or advanced packaging design in a semiconductor or deep-tech environment
Demonstrated expertise in on-die power grid design and package/PCB PDN analysis
Hands-on experience with 2.5D and/or 3D IC packaging technologies, multi-chiplet integration, and interposer/substrate co-design
Proficiency with industry-standard EDA tools for power integrity, PDN simulation, and package design
Ability to work cross-functionally and communicate complex technical trade-offs to diverse stakeholder groups
Strong written and spoken English communication skills