We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon
Develop and execute verification plans for block-level, subsystem-level, and full-chip environments
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations
Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis
Participate in ASIC team interviews
Drive advancement of DV methodologies and improvements
Manage external IP providers and verification partners when needed
Take lead on large and/or complex systems