Дополнительно
Digital systems
Hardware design
Digital logic and electronics
FPGA/ASIC fundamentals
HDL languages (Verilog / SystemVerilog preferred; VHDL optional)
Proficiency in English sufficient to follow instructions and communicate clearly
Ideal profile: recent graduates of technical fields or enthusiasts with relevant practical experience
Project Overview
The project involves creating a dataset of diagram images paired with one of two types of technical artefacts
Diagram + HDL code (Verilog/SystemVerilog)
Diagram + English technical explanation of the diagram
Workload distribution: 50% code-based, 50% description-based
Circuit diagrams
Timing diagrams (waveforms)
State diagrams (finite state machines)
(With a near-even distribution across all three categories.)