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Senior ASIC Emulation Engineer
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K2 Space Corporation·United States - Remote·3 авг.

Senior ASIC Emulation Engineer

🌍 УдалённоSeniorПолная занятость🌐 Глобал
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Наша компания

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an

О роли

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

Чем предстоит заниматься

We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first‑generation silicon and system methodology
Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce
Define and evolve emulation strategy, methodology, and workflows across the ASIC organization
Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability
Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases
Support system‑level testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end‑to‑end workloads
Accelerate overall verification throughput by helping DV team run targeted and high‑value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks
Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug
Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues
Maintain and enhance automation for compile flows, regression management, and continuous integration
Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation
Manage interactions with external IP providers or emulation partners when needed

Наши требования

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
5+ years of experience in ASIC/SoC development, focused on emulation
Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles
Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling
Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++‑based system-level testing
Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI
Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams
Understanding of pre- and post-silicon debug methodologies and correlation workflows
Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards)
Experience with low-power modes and power-aware emulation
Experience with analog/mixed-signal behavioral models in emulation environments
Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs

Мы предлагаем

Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
Export Compliance
As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”

Дополнительно

Base salary range for this role is $170,000 – $250,000 + equity in the company
K
K2 Space Corporation
United States - Remote

ГрейдSenior
ЗанятостьПолная занятость
РегионСША
ФорматУдалённо
ИсточникСкрыто
Опубликовано3 авг.
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